View AM29DL323D_8934030.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 25097 rev: a amendment/ 0 issue date: june 18, 2001 refer to amd?s website (www.amd.com) for the latest information. ds42587 stacked multi-chip package (mcp) flash memory and sram AM29DL323D top boot 32 megabit (4 m x 8-bit/2 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory and 8 mbit (1 mb x 8-bit/512 k x 16-bit) static ram distinctive characteristics mcp features power supply voltage of 2.7 to 3.3 volt high performance ? 85 ns maximum access time package ? 73-ball fbga operating temperature ? ?25c to +85c flash memory features architectural advantages simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations secured silicon (secsi) sector: extra 64 kbyte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. ? customer lockable: can be read, programmed, or erased just like other sectors. once locked, data cannot be changed zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero top boot block manufactured on 0.23 m process technology compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard performance characteristics high performance ? access time as fast 85 ns ? program time: 7 s/word typical utilizing accelerate function ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode minimum 1 million write cycles guaranteed per sector 20 year data retention at 125 c ? reliable operation for the life of the system software features data management software (dms) ? amd-supplied software manages data programming and erasing, enabling eeprom emulation ? eases sector erase limitations supports common flash memory interface (cfi) erase suspend/erase resume ? suspends erase operations to allow programming in same bank data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features any combination of sectors can be erased ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method of resetting the internal state machine to reading array data wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sectors, regardless of sector protect status ? acceleration (acc) function accelerates program timing sector protection ? hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector ? temporary sector unprotect allows changing data in protected sectors in-system sram features power dissipation ? operating: 50 ma maximum ? standby: 25 a maximum ce1s# and ce2s chip select power down features using ce1s# and ce2s data retention supply voltage: 1.5 to 3.3 volt byte data control: lb#s (dq0?dq7), ub#s (dq8?dq15)
2 ds42587 general description am29dl323 features the am29dl323 is a 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. word mode data appears on dq0 ? dq15; byte mode data appears on dq0 ? dq7. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 85 ns. the device is offered in a 73-ball fbga package. standard control pins ? chip enable (ce#f), write en- able (we#), and output enable (oe#) ? control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into two banks. the device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. this releases the system from waiting for the completion of program or erase operations. the AM29DL323D has 8 mb in bank 1 and 24 mb in bank 2. the secured silicon (secsi) sector is an extra 64 kbit sector capable of being permanently locked by amd or customers. the secsi sector indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, customer lockable parts can never be used to re- place a factory locked part. factory locked parts provide several options. the secsi sector may store a secure, random 16 byte esn (electronic serial number). customer lockable parts may utilize the secsi sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. dms (data management software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of eeprom devices. dms will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the flash memory device (or memory de- vices), and more. using dms, user-written software does not need to interface with the flash memory di- rectly. instead, the user's software accesses the flash memory by calling one of only six functions. amd pro- vides this software to simplify system design and software integration efforts. the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via programming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly re- duced in both modes.
ds42587 3 table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . 1 mcp features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 flash memory features . . . . . . . . . . . . . . . . . . . . . 1 architectural advantages . . . . . . . . . . . . . . . . . . . 1 performance characteristics . . . . . . . . . . . . . . . . 1 software features . . . . . . . . . . . . . . . . . . . . . . . . 1 hardware features . . . . . . . . . . . . . . . . . . . . . . . 1 sram features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 2 am29dl323 features . . . . . . . . . . . . . . . . . . . . . . 2 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . 5 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 flash memory block diagram. . . . . . . . . . . . . . . . 6 connection diagram . . . . . . . . . . . . . . . . . . . . . . . 7 special handling instructions for fbga package . 7 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . 8 table 1. device bus operations ? flash word mode, ciof = v ih ; sram word mode, cios = v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. device bus operations ? flash word mode, ciof = v ih ; sram byte mode, cios = v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. device bus operations ? flash byte mode, ciof = v il ; sram byte mode, cios = v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 word/byte configuration . . . . . . . . . . . . . . . . . . . 12 requirements for reading array data . . . . . . . . . 12 writing commands/command sequences . . . . . 12 accelerated program operation . . . . . . . . . . . . 12 autoselect functions . . . . . . . . . . . . . . . . . . . . . 12 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . 13 reset#: hardware reset pin . . . . . . . . . . . . . . . 13 output disable mode . . . . . . . . . . . . . . . . . . . . . . 13 table 4. device bank division . . . . . . . . . . . . . . 13 table 5. sector addresses for top boot sector devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. secsi ? sector addresses for top boot devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . 16 sector/sector block protection and unprotection 16 table 7. top boot sector/sector block addresses for protection/unprotection . . . . . . . 16 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . 16 temporary sector/sector block unprotect . . . . . . 17 figure 1. temporary sector unprotect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2. in-system sector/sector block protect and unprotect algorithms . . . . . . . . . . . 18 secsi (secured silicon) sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 factory locked: secsi sector programmed and protected at the factory . . . . . . . . . . . . . . . . . . 19 customer lockable: secsi sector not programmed or protected at the factory . . . . . 19 hardware data protection . . . . . . . . . . . . . . . . . . 19 low v cc write inhibit . . . . . . . . . . . . . . . . . . . . 19 write pulse ? glitch ? protection . . . . . . . . . . . . . 19 logical inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power-up write inhibit . . . . . . . . . . . . . . . . . . . 20 common flash memory interface (cfi) . . . . . . . 20 table 8. cfi query identification string . . . . . . 20 table 9. system interface string . . . . . . . . . . . 21 table 10. device geometry definition . . . . . . . 21 table 11. primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 command definitions. . . . . . . . . . . . . . . . . . . . . . 23 reading array data . . . . . . . . . . . . . . . . . . . . . . . 23 reset command . . . . . . . . . . . . . . . . . . . . . . . . . 23 autoselect command sequence . . . . . . . . . . . . . 23 enter secsi sector/exit secsi sector command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 byte/word program command sequence . . . . . 24 unlock bypass command sequence . . . . . . . . 24 figure 3. program operation . . . . . . . . . . . . . . . 25 chip erase command sequence . . . . . . . . . . . . 25 sector erase command sequence . . . . . . . . . . . 25 erase suspend/erase resume commands . . . . 26 figure 4. erase operation . . . . . . . . . . . . . . . . . 26 table 12. ds42587 command definitions . . . . 27 write operation status . . . . . . . . . . . . . . . . . . . . . 28 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. data# polling algorithm . . . . . . . . . . . 28 ry/by#: ready/busy# . . . . . . . . . . . . . . . . . . . . . 29 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. toggle bit algorithm . . . . . . . . . . . . . . 29 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . 30 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . 30 dq5: exceeded timing limits . . . . . . . . . . . . . . . 30 dq3: sector erase timer . . . . . . . . . . . . . . . . . . 30 table 13. write operation status . . . . . . . . . . . 31 absolute maximum ratings. . . . . . . . . . . . . . . . . 32 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32 industrial (i) devices . . . . . . . . . . . . . . . . . . . . . 32 v cc f/v cc s supply voltage . . . . . . . . . . . . . . . . . 32 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . 33 sram dc and operating characteristics. . . . . . 34 zero-power flash . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) . . . . . . . . . . . . . 35 figure 10. typical i cc1 vs. frequency . . . . . . . . 35 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. test setup . . . . . . . . . . . . . . . . . . . . 36 table 14. test specifications . . . . . . . . . . . . . . 36
4 ds42587 key to switching waveforms. . . . . . . . . . . . . . . 36 figure 12. input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 sram ce#s timing . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. timing diagram for alternating between sram to flash. . . . . . . . . . . . . . . . . . 37 flash read-only operations . . . . . . . . . . . . . . . . 38 figure 14. read operation timings . . . . . . . . . 38 hardware reset (reset#) . . . . . . . . . . . . . . . . . 39 figure 15. reset timings . . . . . . . . . . . . . . . . . 39 flash word/byte configuration (ciof) . . . . . . . . . 40 figure 16. ciof timings for read operations . 40 figure 17. ciof timings for write operations. . 40 flash erase and program operations . . . . . . . . . 41 figure 18. program operation timings. . . . . . . 42 figure 19. accelerated program timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . 44 figure 23. toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . 45 figure 24. dq2 vs. dq6 . . . . . . . . . . . . . . . . . . 45 temporary sector/sector block unprotect . . . . . . 46 figure 25. temporary sector/sector block unprotect timing diagram . . . . . . . . . . . . . . . . 46 figure 26. sector/sector block protect and unprotect timing diagram. . . . . . . . . . . . . . . . . 47 alternate ce#f controlled erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 27. flash alternate ce#f controlled write (erase/program) operation timings . . . . . . . . . 49 sram read cycle . . . . . . . . . . . . . . . . . . . . . . . 50 figure 28. sram read cycle ? address controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 29. sram read cycle . . . . . . . . . . . . . . 51 sram write cycle . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. sram write cycle ? we# control . . 52 figure 31. sram write cycle ? ce1#s control. 53 figure 32. sram write cycle ? ub#s and lb#s control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 flash erase and programming performance . . . 55 flash latchup characteristics. . . . . . . . . . . . . . . 55 package pin capacitance . . . . . . . . . . . . . . . . . . 55 flash data retention . . . . . . . . . . . . . . . . . . . . . 55 sram data retention . . . . . . . . . . . . . . . . . . . . . . 56 figure 33. ce1#s controlled data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 34. ce2s controlled data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 57 flb073 ? 73-ball fine-pitch grid array 8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 58 revision a (june 18, 2001) . . . . . . . . . . . . . . . . . 58
ds42587 5 product selector guide mcp block diagram part number ds42587 standard voltage range: v cc = 2.7 ? 3.3 v flash memory sram max access time (ns) 85 85 ce# access (ns) 85 85 oe# access (ns) 40 45 v ss /v ssq v cc s/v ccq reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb#s ub#s ciof wp#/acc ce2s sa cios 8 m bit static ram 32 m bit flash memory dq0 to dq15/a ? 1 dq0 to dq15/a ? 1 dq0 to dq15/a ? 1 a0 to a20 a0 to a20 a0 to a19 a ? 1 a0 to a18
6 ds42587 flash memory block diagram v cc v ss upper bank address a0 ? a20 reset# we# ce# byte# dq0 ? dq15 wp#/acc state control & command register ry/by# upper bank x-decoder y-decoder latches and control logic oe# byte# dq0 ? dq15 lower bank y-decoder x-decoder latches and control logic lower bank address oe# byte# status control a0 ? a20 a0 ? a20 a0 ? a20 a0 ? a20 dq0 ? dq15 dq0 ? dq15
ds42587 7 connection diagram special handling instructions for fbga package special handling is required for flash memory prod- ucts in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa dq15/a-1 dq7 dq14 a15 nc nc a16 ciof v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga top view
8 ds42587 pin description a0 ? a18 = 19 address inputs (common) a-1, a19 ? a20 = 3 address inputs (flash) sa = highest order address pin (sram) byte mode dq0 ? dq15 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce#s = chip enable (sram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub#s = upper byte control (sram) lb#s = lower byte control (sram) ciof = i/o configuration (flash) ciof = v ih = word mode (x16), ciof = v il = byte mode (x8) cios = i/o configuration (sram) cios = v ih = word mode (x16), cios = v il = byte mode (x8) reset# = hardware reset pin, active low wp#/acc = hardware write protect/ acceleration pin (flash) v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc s = sram power supply v ss = device ground (common) nc = pin not connected internally logic symbol ordering information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. tables 1 through 3 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections de- scribe each of these operations in further detail. 19 16 or 8 dq0 ? dq15 a0 ? a18 ce#f oe# we# reset# ub#s ry/by# wp#/acc sa a-1, a19 ? a20 lb#s ciof cios ce1#s ce2s valid combination order number package marking ds42587 ds42587
ds42587 9 table 1. device bus operations ? flash word mode, ciof = v ih ; sram word mode, cios = v cc legend: l = logic low = v il , h = logic high = v ih , v id = 8.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 4. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 5. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection?. if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa lb#s ub#s reset# wp#/acc (note 3) dq0 ? dq7 dq8 ? dq15 read from flash l hx lh x x x h l/h d out d out xl write to flash l hx h l x x x h (note 3) d in d in xl standby v cc 0.3 v hx xx x x x v cc 0.3 v hhigh-zhigh-z xl output disable hlh hh x l x h l/h high-z high-z hh x x l l hx hh x x x xl flash hardware reset x hx x x x x x l l/h high-z high-z xl sector protect (note 4) l hx hl x x x v id l/h d in x xl sector unprotect (note 4) l hx hl x x x v id (note 5) d in x xl temporary sector unprotect x hx xx x x x v id (note 5) d in high-z xl read from sram h l h l h x ll hx d out d out hl high-z d out lh d out high-z write to sram h l h x l x ll hx d in d in hl high-z d in lh d in high-z
10 ds42587 table 2. device bus operations ? flash word mode, ciof = v ih ; sram byte mode, cios = v ss legend: l = logic low = v il , h = logic high = v ih , v id = 8.5 ? 12.5 v, v hh = 9.0 0.5 v, x = don ? t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don ? t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ? sector/sector block protection and unprotection ? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ? sector/sector block protection and unprotection ? . if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa lb#s (note 3) ub#s (note 3) reset# wp#/acc (note 4) dq0 ? dq7 dq8 ? dq15 read from flash l hx lh x x x h l/h d out d out xl write to flash l hx h l l x x h (note 3) d in d in xl standby v cc 0.3 v hx xx x x x v cc 0.3 v h high-z high-z xl output disable hlh hh x l x h l/h high-z high-z hh x x l l hx hh x x x xl flash hardware reset x hx x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hl x x x v id l/h d in x xl sector unprotect (note 5) l hx hl x x x v id (note 6) d in x xl temporary sector unprotect x hx xx x x x v id (note 6) d in high-z xl read from sram h l h l h sa x x h x d out high-z write to sram h l h x l sa x x h x d in high-z
ds42587 11 table 3. device bus operations ? flash byte mode, ciof = v il ; sram byte mode, cios = v ss legend: l = logic low = v il , h = logic high = v ih , v id = 8.5 ? 12.5 v, v hh = 9.0 0.5 v, x = don ? t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don ? t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ? sector/sector block protection and unprotection ? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ? sector/sector block protection and unprotection ? . if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s dq15/ a ? 1 oe# we# sa lb#s (note 3) ub#s (note 3) reset# wp#/acc (note 4) dq0 ? dq7 dq8 ? dq15 read from flash l hx a ? 1lh x x x h l/h d out high-z xl write to flash l hx a ? 1hl x x x h (note 3) d in high-z xl standby v cc 0.3 v hx xx x x x v cc 0.3 v h high-z high-z xl output disable hlh xhhx l x h l/h high-z high-z hhxx x l l hx a ? 1hh x x x xl flash hardware reset x hx x x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hl x x x v id l/h d in x xl sector unprotect (note 5) l hx hl x x x v id (note 6) d in x xl temporary sector unprotect x hx xx x x x v id (note 6) d in high-z xl read from sram hlhxlhsax x h x d out high-z write to sram h l h x x l sa x x h x d in high-z
12 ds42587 word/byte configuration the ciof pin controls whether the device data i/o pins operate in the byte or word configuration. if the ciof pin is set at logic ? 1 ? , the device is in word configura- tion, dq0 ? dq15 are active and controlled by ce# and oe#. if the ciof pin is set at logic ? 0 ? , the device is in byte configuration, and only data i/o pins dq0 ? dq7 are active and controlled by ce# and oe#. the data i/o pins dq8 ? dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce#f and oe# pins to v il . ce#f is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the ciof pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. see ? requirements for reading array data ? for more information. refer to the ac flash read-only opera- tions table for timing specifications and to figure 14 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce#f to v il , and oe# to v ih . for program operations, the ciof pin determines whether the device accepts program data in bytes or words. refer to ? word/byte configuration ? for more information. the device features an unlock bypass mode to facil- itate faster programming. once a bank enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ? word/byte configuration ? section has details on pro- gramming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. tables 5 ? 6 indicate the address space that each sector occupies. the device address space is divided into two banks: bank 1 con- tains the boot/parameter sectors, and bank 2 contains the larger, code sectors of uniform size. a ? bank ad- dress ? is the address bits required to uniquely select a bank. similarly, a ? sector address ? is the address bits required to uniquely select a sector. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated pro- gramming, or device damage may result. in addition, the wp#/acc pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7 ? dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 and i cc7 in the dc characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.
ds42587 13 standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#f and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce#f and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the de- vice requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#f, we#, and oe# control signals. standard ad- dress access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the de- vice draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby cur- rent will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ? 0 ? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not ex- ecuting (ry/by# pin is ? 1 ? ), the reset operation is completed within a time of t ready (not during embed- ded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 15 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 4. device bank division device part number bank 1 bank 2 megabits sector sizes megabits sector sizes AM29DL323D 8 mbit eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword 24 mbit forty-eight 64 kbyte/32 kword
14 ds42587 table 5. sector addresses for top boot sector devices AM29DL323Dt sector sector address a20 ? a12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 2 sa0 000000xxx 64/32 000000h ? 00ffffh 000000h ? 07fffh sa1 000001xxx 64/32 010000h ? 01ffffh 008000h ? 0ffffh sa2 000010xxx 64/32 020000h ? 02ffffh 010000h ? 17fffh sa3 000011xxx 64/32 030000h ? 03ffffh 018000h ? 01ffffh sa4 000100xxx 64/32 040000h ? 04ffffh 020000h ? 027fffh sa5 000101xxx 64/32 050000h ? 05ffffh 028000h ? 02ffffh sa6 000110xxx 64/32 060000h ? 06ffffh 030000h ? 037fffh sa7 000111xxx 64/32 070000h ? 07ffffh 038000h ? 03ffffh sa8 001000xxx 64/32 080000h ? 08ffffh 040000h ? 047fffh sa9 001001xxx 64/32 090000h ? 09ffffh 048000h ? 04ffffh sa10 001010xxx 64/32 0a0000h ? 0affffh 050000h ? 057fffh sa11 001011xxx 64/32 0b0000h ? 0bffffh 058000h ? 05ffffh sa12 001100xxx 64/32 0c0000h ? 0cffffh 060000h ? 067fffh sa13 001101xxx 64/32 0d0000h ? 0dffffh 068000h ? 06ffffh sa14 001110xxx 64/32 0e0000h ? 0effffh 070000h ? 077fffh sa15 001111xxx 64/32 0f 0000h ? 0fffffh 078000h ? 07ffffh sa16 010000xxx 64/32 100000h ? 10ffffh 080000h ? 087fffh sa17 010001xxx 64/32 110000h ? 11ffffh 088000h ? 08ffffh sa18 010010xxx 64/32 120000h ? 12ffffh 090000h ? 097fffh sa19 010011xxx 64/32 130000h ? 13ffffh 098000h ? 09ffffh sa20 010100xxx 64/32 140000h ? 14ffffh 0a0000h ? 0a7fffh sa21 010101xxx 64/32 150000h ? 15ffffh 0a8000h ? 0affffh sa22 010110xxx 64/32 160000h ? 16ffffh 0b0000h ? 0b7fffh sa23 010111xxx 64/32 170000h ? 17ffffh 0b8000h ? 0bffffh sa24 011000xxx 64/32 180000h ? 18ffffh 0c0000h ? 0c7fffh sa25 011001xxx 64/32 190000h ? 19ffffh 0c8000h ? 0cffffh sa26 011010xxx 64/32 1a0000h ? 1affffh 0d0000h ? 0d7fffh sa27 011011xxx 64/32 1b0000h ? 1bffffh 0d8000h ? 0dffffh sa28 011100xxx 64/32 1c0000h ? 1cffffh 0e0000h ? 0e7fffh sa29 011101xxx 64/32 1d0000h ? 1dffffh 0e8000h ? 0effffh sa30 011110xxx 64/32 1e0000h ? 1effffh 0f0000h ? 0f7fffh sa31 011111xxx 64/32 1f 0000h ? 1fffffh 0f8000h ? 0fffffh sa32 100000xxx 64/32 200000h ? 20ffffh 100000h ? 107fffh sa33 100001xxx 64/32 210000h ? 21ffffh 108000h ? 10ffffh sa34 100010xxx 64/32 220000h ? 22ffffh 110000h ? 117fffh sa35 100011xxx 64/32 230000h ? 23ffffh 118000h ? 11ffffh sa36 100100xxx 64/32 240000h ? 24ffffh 120000h ? 127fffh sa37 100101xxx 64/32 250000h ? 25ffffh 128000h ? 12ffffh sa38 100110xxx 64/32 260000h ? 26ffffh 130000h ? 137fffh sa39 100111xxx 64/32 270000h ? 27ffffh 138000h ? 13ffffh sa40 101000xxx 64/32 280000h ? 28ffffh 140000h ? 147fffh sa41 101001xxx 64/32 290000h ? 29ffffh 148000h ? 14ffffh sa42 101010xxx 64/32 2a0000h ? 2affffh 150000h ? 157fffh sa43 101011xxx 64/32 2b0000h ? 2bffffh 158000h ? 15ffffh sa44 101100xxx 64/32 2c0000h ? 2cffffh 160000h ? 167fffh sa45 101101xxx 64/32 2d0000h ? 2dffffh 168000h ? 16ffffh sa46 101110xxx 64/32 2e0000h ? 2effffh 170000h ? 177fffh sa47 101111xxx 64/32 2f 0000h ? 2fffffh 178000h ? 17ffffh
ds42587 15 note: the address range is a20:a-1 in byte mode (ciof=v il ) or a20:a0 in word mode (ciof=v ih ). the bank address bits are a20 and a19 for AM29DL323Dt. table 6. secsi ? sector addresses for top boot devices bank 1 sa48 110000xxx 64/32 300000h ? 30ffffh 180000h ? 187fffh sa49 110001xxx 64/32 310000h ? 31ffffh 188000h ? 18ffffh sa50 110010xxx 64/32 320000h ? 32ffffh 190000h ? 197fffh sa51 110011xxx 64/32 330000h ? 33ffffh 198000h ? 19ffffh sa52 110100xxx 64/32 340000h ? 34ffffh 1a0000h ? 1a7fffh sa53 110101xxx 64/32 350000h ? 35ffffh 1a8000h ? 1affffh sa54 110110xxx 64/32 360000h ? 36ffffh 1b0000h ? 1b7fffh sa55 110111xxx 64/32 370000h ? 37ffffh 1b8000h ? 1bffffh sa56 111000xxx 64/32 380000h ? 38ffffh 1c0000h ? 1c7fffh sa57 111001xxx 64/32 390000h ? 39ffffh 1c8000h ? 1cffffh sa58 111010xxx 64/32 3a0000h ? 3affffh 1d0000h ? 1d7fffh sa59 111011xxx 64/32 3b0000h ? 3bffffh 1d8000h ? 1dffffh sa60 111100xxx 64/32 3c0000h ? 3cffffh 1e0000h ? 1e7fffh sa61 111101xxx 64/32 3d0000h ? 3dffffh 1e8000h ? 1effffh sa62 111110xxx 64/32 3e0000h ? 3effffh 1f0000h ? 1f7fffh sa63 111111000 8/4 3f0000h ? 3f1fffh 1f8000h ? 1f8fffh sa64 111111001 8/4 3f2000h ? 3f3fffh 1f9000h ? 1f9fffh sa65 111111010 8/4 3f4000h ? 3f5fffh 1fa000h ? 1fafffh sa66 111111011 8/4 3f 6000h ? 3f7fffh 1fb000h ? 1fbfffh sa67 111111100 8/4 3f 8000h ? 3f9fffh 1fc000h ? 1fcfffh sa68 111111101 8/4 3fa 000h ? 3fbfffh 1fd000h ? 1fdfffh sa69 111111110 8/4 3fc 000h ? 3fdfffh 1fe000h ? 1fefffh sa70 111111111 8/4 3fe 000h ? 3fffffh 1ff000h ? 1fffffh device sector address a20 ? a12 sector size (x8) address range (x16) address range AM29DL323Dt 111111xxx 64/32 3f 0000h ? 3fffffh 1f8000h ? 1ffffh table 5. sector addresses for top boot sector devices (continued) AM29DL323Dt sector sector address a20 ? a12 sector size (kbytes/kwords) (x8) address range (x16) address range
16 ds42587 autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7 ? dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be programmed with its corresponding programming al- gorithm. however, the autoselect codes can also be accessed in-system through the command register. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 12. this method does not require v id . refer to the autoselect com- mand sequence section for more information. sector/sector block protection and unprotection (note: for the following discussion, the term ? sector ? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table 7). table 7. top boot sector/sector block addresses for protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. note that the sector unprotect algorithm un- protects all sectors in parallel. all previously protected sectors must be individually re-protected. to change data in protected sectors efficiently, the temporary sector un protect function is available. see ? temporary sector/sector block unprotect ? . sector protection and unprotection can be imple- mented as follows. sector protection and unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 26 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is pro- tected or unprotected. see the autoselect mode section for details. write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two ? outermost ? 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in ? sector/sector block protection and unprotection ? . the two outermost 8 kbyte boot sectors are the two sectors containing the lowest addresses in the bottom-boot-configured device. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the two outermost 8 kbyte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in ? sec- tor/sector block protection and unprotection ? . sector a20 ? a12 sector/ sector block size sa0 000000xxx 64 kbytes sa1-sa3 000001xxx, 000010xxx 000011xxx 192 (3x64) kbytes sa4-sa7 0001xxxxx 256 (4x64) kbytes sa8-sa11 0010xxxxx 256 (4x64) kbytes sa12-sa15 0011xxxxx 256 (4x64) kbytes sa16-sa19 0100xxxxx 256 (4x64) kbytes sa20-sa23 0101xxxxx 256 (4x64) kbytes sa24-sa27 0110xxxxx 256 (4x64) kbytes sa28-sa31 0111xxxxx 256 (4x64) kbytes sa32-sa35 1000xxxxx 256 (4x64) kbytes sa36-sa39 1001xxxxx 256 (4x64) kbytes sa40-sa43 1010xxxxx 256 (4x64) kbytes sa44-sa47 1011xxxxx 256 (4x64) kbytes sa48-sa51 1100xxxxx 256 (4x64) kbytes sa52-sa55 1101xxxxx 256 (4x64) kbytes sa56-sa59 1110xxxxx 256 (4x64) kbytes sa60-sa62 111100xxx, 111101xxx, 111110xxx 192 (4x64) kbytes sa63 11111 1000 8 kbytes sa64 11111 1001 8 kbytes sa65 11111 1010 8 kbytes sa66 111111011 8 kbytes sa67 111111100 8 kbytes sa68 111111101 8 kbytes sa69 111111110 8 kbytes sa70 111111111 8 kbytes sector a20 ? a12 sector/ sector block size
ds42587 17 note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. temporary sector/sector block unprotect (note: for the following discussion, the term ? sector ? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table 7). this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id (8.5 v ? 12.5 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pro- tected sectors are protected again. figure 1 shows the algorithm, and figure 25 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again.
18 ds42587 note: the term ? sector ? in the figure applies to both sectors and sector blocks. figure 2. in-system sector/sector block protect and unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
ds42587 19 secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 64 kbytes in length, and uses a secsi sector indicator bit to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi sector indicator bit permanently set to a ? 1. ? the customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. the customer-lockable version has the secsi sector indicator bit permanently set to a ? 0. ? thus, the secsi sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the system accesses the secsi sector through a command sequence (see ? enter secsi sector/exit secsi sector command sequence ? ). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is pro- tected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is available preprogrammed with a random, se- cure esn only in devices that have an esn, the top boot starting ad- dress of the esn will be at the bottom of the lowest 8 kbyte boot sector at addresses 1f8000h ? 1f8007h in word mode (or addresses 3f0000h ? 3f000fh in byte mode). customer lockable: secsi sector not programmed or protected at the factory if the security feature is not required, the secsi sector can be treated as an additional flash memory space, expanding the size of the available flash array by 64 kbytes. the secsi sector can be read, programmed, and erased as often as required. note that the acceler- ated programming (acc) and unlock bypass functions are not available when programming the secsi sector. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. write the three-cycle enter secsi sector region command sequence, and then use the alternate method of sector protection described in the ? sec- tor/sector block protection and unprotection ? . once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region command sequence to return to reading and writing the remainder of the array. the secsi sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 12 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subse- quent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ? glitch ? protection noise pulses of less than 5 ns (typical) on oe#, ce#f or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce#f = v ih or we# = v ih . to initiate a write cycle,
20 ds42587 ce#f and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce#f = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to reading array data on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the sys- tem can read cfi information at the addresses given in tables 8 ? 11. to terminate reading cfi data, the sys- tem must write the reset command. the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8 ? 11. the system must write the reset command to return the de- vice to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/prod- ucts/nvd/overview/cfi.html. alternatively, contact an amd representative for copies of these documents. table 8. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ? qry ? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
ds42587 21 table 9. system interface string table 10. device geometry definition addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 001eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
22 ds42587 table 11. primary vendor-specific extended query note: the number of sectors in bank 2 is device dependent, am29dl323 = 30h. addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ? pri ? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 94h 00xxh (see note) simultaneous operation 00 = not supported, x= number of sectors in bank 2 (uniform bank) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device
ds42587 23 command definitions writing specific address and data commands or se- quences into the command register initiates device operations. table 12 defines the valid register com- mand sequences. writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#f, whichever happens later. all data is latched on the rising edge of we# or ce#f, whichever hap- pens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands sec- tion for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the flash read-only operations table provides the read parameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don ? t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to reading array data. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 12 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autoselect mode. the system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: a read cycle at address (ba)xx00h (where ba is the bank address) returns the manufacturer code. a read cycle at address (ba)xx01h in word mode (or (ba)xx02h in byte mode) returns the device code. a read cycle to an address containing a sector ad- dress (sa) within the same bank, and the address 02h on a7 ? a0 in word mode (or the address 04h on a6 ? a-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (refer to ta- bles 5 ? 6 for valid sector addresses). the system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in erase suspend).
24 ds42587 enter secsi sector/exit secsi sector command sequence the system can access the secsi sector region by is- suing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the device to nor- mal operation. table 12 shows the address and data requirements for both command sequences. see also ? secsi (secured silicon) sector flash memory re- gion ? for further information. note that a hardware reset (reset#=v il ) will reset the device to reading array data. byte/word program command sequence the system may program the device by word or byte, depending on the state of the ciof pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. table 12 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write oper- ation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ? 0 ? back to a ? 1. ? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still ? 0. ? only erase operations can convert a ? 0 ? to a ? 1. ? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 12 shows the require- ments for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the reading array data. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 3 illustrates the algorithm for the program oper- ation. refer to the flash erase and program operations table in the ac characteristics section for parameters, and figure 18 for timing diagrams.
ds42587 25 figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 12 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the flash erase and program operations tables in the ac characteristics section for parameters, and figure 20 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 12 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to reading array data. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can de- termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 12 for program command sequence.
26 ds42587 refer to the write operation status section for infor- mation on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the flash erase and program operations tables in the ac characteristics section for parameters, and figure 20 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. however, when the erase suspend command is writ- ten during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ? erase sus- pends ? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7 ? dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the re- sume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 4. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 12 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
ds42587 27 table 12. ds42587 command definitions legend: x = don ? t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce#f pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce#f pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20 ? a12 uniquely select any sector. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. notes: 1. see tables 1 through 3 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15 ? dq8 are don ? t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20 ? a11 are don ? t cares. 6. no unlock or command cycles required when bank is in read mode. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id, device id, or secsi sector factory protect information. data bits dq15 ? dq8 are don ? t care. see the autoselect command sequence section for more information. 9. the data is 80h for factory locked and 00h for not factory locked. 10. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. the erase resume command is valid only during the erase command sequence (note 1) cycles bus cycles (notes 2 ? 5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id word 4 555 aa 2aa 55 (ba)555 90 (ba)x01 byte aaa 555 (ba)aaa (ba)x02 secsi sector factory protect (note 9) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 81/01 byte aaa 555 (ba)aaa (ba)x06 sector protect verify (note 10) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/01 byte aaa 555 (ba)aaa (sa)x04 enter secsi sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secsi sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 ba 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 ba b0 erase resume (note 14) 1 ba 30 cfi query (note 15) word 1 55 98 byte aa
28 ds42587 write operation status the device provides several bits to determine the sta- tus of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 13 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a pro- gram or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host sys- tem whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the em- bedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to reading array data. during the embedded erase algorithm, data# polling produces a ? 0 ? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ? 1 ? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the bank returns to reading array data. if not all se- lected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0 ? dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0 ? dq6 may be still invalid. valid data on dq0 ? dq7 will appear on suc- cessive read cycles. table 13 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 22 in the ac characteristics section shows the data# polling timing diagram. figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7 ? dq0 addr = va read dq7 ? dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ? 1 ? because dq7 may change simultaneously with dq5.
ds42587 29 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is reading array data, the standby mode, or one of the banks is in the erase-sus- pend-read mode. table 13 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce#f to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 13 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 23 in the ? ac characteristics ? section shows the toggle bit timing diagrams. figure 24 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 6. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7 ? dq0 toggle bit = toggle? read dq7 ? dq0 twice read dq7 ? dq0 note: the system should recheck the toggle bit even if dq5 = ? 1 ? because the toggle bit may stop toggling as dq5 changes to ? 1. ? see the subsections on dq6 and dq2 for more information.
30 ds42587 dq2: toggle bit ii the ? toggle bit ii ? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce#f to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 13 to compare out- puts for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ? dq2: toggle bit ii ? explains the algorithm. see also the dq6: toggle bit i subsection. figure 23 shows the toggle bit timing diagram. figure 24 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7 ? dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7 ? dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ? 1, ? indicating that the program or erase cycle was not successfully completed. the device may output a ? 1 ? on dq5 if the system tries to program a ? 1 ? to a location that was previously pro- grammed to ? 0. ? only an erase operation can change a ? 0 ? back to a ? 1. ? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ? 1. ? under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ? 0 ? to a ? 1. ? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ? 1, ? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ? 0, ? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 13 shows the status of dq3 relative to the other status bits.
ds42587 31 table 13. write operation status notes: 1. dq5 switches to ? 1 ? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
32 ds42587 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ? 55 c to +125 c ambient temperature with power applied . . . . . . . . . . . . . . ? 25 c to +85 c voltage with respect to ground v cc f/v cc s (note 1) . . . . . . . . . . . . ? 0.3 v to +4.0 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ? 0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . ? 0.5 v to +10.5 v all other pins (note 1) . . . . . . ? 0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ? 0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ? 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 7. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8. 2. minimum dc input voltage on pins oe#, reset#, and wp#/acc is ? 0.5 v. during voltage transitions, oe#, wp#/acc, and reset# may overshoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 7. maximum dc input voltage on pin reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ? 25 c to +85 c v cc f/v cc s supply voltage v cc f/v cc s for standard voltage range . . 2.7 v to 3.3 v operating ranges define those limits between which the func- tionality of the device is guaranteed. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ? 0.5 v 20 ns ? 2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
ds42587 33 dc characteristics cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit reset# input load current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i lia acc input leakage current v cc = v cc max , wp#/acc = v acc max 35 a i cc1 f flash v cc active read current (notes 1, 2) ce#f = v il , oe# = v ih , byte mode 5 mhz 10 16 ma 1 mhz 2 4 ce#f = v il , oe# = v ih , word mode 5 mhz 10 16 1 mhz 2 4 i cc2 f flash v cc active write current (notes 2, 3) ce#f = v il , oe# = v ih , we# = v il 15 30 ma i cc3 fflash v cc standby current (note 2) v cc f = v cc max , ce#f, reset#, wp#/acc = v cc f 0.3 v 0.2 5 a i cc4 fflash v cc reset current (note 2) v cc f = v cc max , reset# = v ss 0.3 v, wp#/acc = v cc f 0.3 v 0.2 5 a i cc5 f flash v cc current automatic sleep mode (notes 2, 4) v cc f = v cc max , v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 f flash v cc active read-while-program current (notes 1, 2) ce#f = v il , oe# = v ih byte 21 45 ma word 21 45 i cc7 f flash v cc active read-while-erase current (notes 1, 2) ce#f = v il , oe# = v ih byte 21 45 ma word 21 45 i cc8 f flash v cc active program-while-erase-suspended current (notes 2, 5) ce#f = v il , oe#f = v ih 17 35 ma i acc acc accelerated program current, word or byte ce#f = v il , oe# = v ih acc pin 5 10 ma v cc pin 15 30 ma i cc1 ssram v cc active current v cc s = v cc max , ce1#s = v il , ce2s = v ih 10 mhz 45 ma i cc2 ssram v cc active current ce1#s = 0.2 v, ce2s = v cc s ? 0.2v 10 mhz 45 ma 1 mhz 5 i cc3 ssram v cc standby current 1) ce1#s = v ih , ce2s = v ih 2) ce2s = v il 0.3 ma i cc4 ssram v cc standby current ce1#s v cc s ? 0.2v, ce2s v cc s ? 0.2v 25 a i cc5 ssram v cc standby current ce2s 0.2v 25 a v il input low voltage ? 0.2 0.8 v v ih input high voltage 2.4 v cc + 0.2 v
34 ds42587 notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. v hh voltage for wp#/acc program acceleration and sector protection/unprotection 8.5 9.5 v v id voltage for sector protection, autoselect and temporary sector unprotect 8.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc f = v cc s = v cc min 0.45 v v oh1 output high voltage i oh = ? 2.0 ma, v cc f = v cc s = v cc min 0.85 x v cc v v oh2 i oh = ? 100 a, v cc = v cc min v cc ? 0.4 v lko flash low v cc lock-out voltage (note 5) 2.3 2.5 v sram dc and operating characteristics parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ? 1.0 1.0 a i lo output leakage current ce1#s = v ih , ce2s = v il or oe# = v ih or we# = v il , v io = v ss to v cc ? 1.0 1.0 a i cc operating power supply current i io = 0 ma, ce1#s = v il , ce2s = we# = v ih , v in = v ih or v il 3ma i cc1 s average operating current cycle time = 1 s, 100% duty, i io = 0 ma, ce1#s 0.2 v, ce2 v cc ? 0.2 v, v in 0.2 v or v in v cc ? 0.2 v 5ma i cc2 s average operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih 45 ma v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = ? 1.0 ma 2.4 v i sb standby current (ttl) ce1#s = v ih , ce2 = v il , other inputs = v ih or v il 0.3 ma i sb1 standby current (cmos) ce1#s v cc ? 0.2 v, ce2 v cc ? 0.2 v (ce1#s controlled) or ce2 0.2 v (ce2s controlled), cios = v ss or v cc , other input = 0 ~ v cc 25 a dc characteristics (continued) cmos compatible parameter symbol parameter description test conditions min typ max unit
ds42587 35 dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma note: t = 25 c figure 10. typical i cc1 vs. frequency 2.7 v 3.3 v 4 6 12
36 ds42587 test conditions table 14. test specifications key to switching waveforms note: diodes are in3064 or equivalent figure 11. test setup 2.7 k ? c l 6.2 k ? 3.3 v device under te s t test condition 85 ns unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 ? 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h don ? t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 12. input waveforms and measurement levels
ds42587 37 ac characteristics sram ce#s timing figure 13. timing diagram for alternating between sram to flash parameter description test setup speed unit jedec std 85 ? t ccr ce#s recover time ? min 0 ns e#f t ccr t ccr e1#s e2s t ccr t ccr
38 ds42587 ac characteristics flash read-only operations notes: 1. not 100% tested. 2. see figure 11 and table 14 for test specifications. parameter description test setup 85 ns speed unit jedec std min max t avav t rc read cycle time (note 1) 85 ns t avqv t acc address to output delay ce#f, oe# = v il 85 ns t elqv t ce chip enable to output delay oe# = v il 85 ns t glqv t oe output enable to output delay 40 ns t ehqz t df chip enable to output high z (note 1) 16 ns t ghqz t df output enable to output high z (note 1) 16 ns t axqx t oh output hold time from addresses, ce#f or oe#, whichever occurs first 0ns t oeh output enable hold time (note 1) read 0 ns toggle and data# polling 10 ns t oh t ce outputs we# addresses ce#f oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
ds42587 39 ac characteristics hardware reset (reset#) note: not 100% tested. parameter description 85 ns unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#f, oe# t rh ce#f, oe# reset timings during embedded algorithms reset# t rp t rb figure 15. reset timings
40 ds42587 ac characteristics flash word/byte configuration (ciof) parameter 85 ns speed jedec std description min typ max unit t elfl /t elfh ce#f to ciof switching low or high 5 ns t flqz ciof switching low to output high z 30 ns t fhqv ciof switching high to output active 85 ns dq15 output data output (dq0 ? dq7) ce#f oe# ciof t elfl dq0 ? dq14 data output (dq0 ? dq14) dq15/a-1 address input t flqz ciof switching from word to byte mode dq15 output data output (dq0 ? dq7) ciof t elfh dq0 ? dq14 data output (dq0 ? dq14) dq15/a-1 address input t fhqv ciof switching from byte to word mode figure 16. ciof timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 17. ciof timings for write operations ce#f we# ciof the falling edge of the last we# signal t hold (t ah ) t set (t as )
ds42587 41 ac characteristics flash erase and program operations notes: 1. not 100% tested. 2. see the ? flash erase and programming performance ? section for more information. parameter 85 ns speed unit jedec std description min typ max t avav t wc write cycle time (note 1) 85 ns t avwl t as address setup time (we# to address) 0 ns t aso address setup time to oe# or ce#f low during toggle bit polling 15 ns t wlax t ah address hold time (we# to address) 45 ns t aht address hold time from ce#f or oe# high during toggle bit polling 0ns t dvwh t ds data setup time 45 ns t whdx t dh data hold time 0 ns t oeh oe# hold time read 0 ns toggle and data# polling 10 ns t oeph output enable high during toggle bit polling 20 20 20 ns t ghel t ghel read recovery time before write (oe# high to ce#f low) 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) 0 ns t wlel t ws we# setup time (ce#f to we#) 0 ns t elwl t cs ce#f setup time (we# to ce#f) 0 ns t ehwh t wh we# hold time (ce#f to we#) 0 ns t wheh t ch ce#f hold time (ce#f to we#) 0 ns t wlwh t wp write pulse width 35 ns t eleh t cp ce#f pulse width 35 ns t whdl t wph write pulse width high 30 ns t sr/w latency between read and write operations 0 ns t whwh1 t whwh1 programming operation (note 2) byte 5 s word 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) 4s t whwh2 t whwh2 sector erase operation (note 2) 0.7 sec t vcs v cc f setup time (note 1) 50 s t rb write recovery time from ry/by# 0 ns t busy program/erase valid to ry/by# delay 90 ns
42 ds42587 ac characteristics figure 19. accelerated program timing diagram oe# we# ce#f v cc f data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa otes: . pa = program address, pd = program data, d out is the true data at the program address. . illustration shows device in word mode. figure 18. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
ds42587 43 ac characteristics oe# ce#f addresses v cc f we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy otes: . sa = sector address (for sector erase), va = valid address for reading status data (see ? write operation status ? ). . these waveforms are for the word mode. figure 20. chip/sector erase operation timings
44 ds42587 ac characteristics oe# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce#f controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w ce#f figure 21. back-to-back read/write cycle timings we# ce#f oe# high z t oe high z dq7 dq0 ? dq6 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 22. data# polling timings (during embedded algorithms)
ds42587 45 ac characteristics oe# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# ce#f note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 23. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce#f to toggle dq2 and dq6. figure 24. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
46 ds42587 ac characteristics temporary sector/sector block unprotect note: not 100% tested. parameter 85 ns speed unit jedec std description t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector/sector block unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector/sector block unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce#f we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 25. temporary sector/sector block unprotect timing diagram
ds42587 47 ac characteristics sector/sector block protect: 150 s, sector/sector block unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce#f we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 26. sector/sector block protect and unprotect timing diagram
48 ds42587 ac characteristics alternate ce#f controlled erase and program operations notes: 1. not 100% tested. 2. see the ? flash erase and programming performance ? section for more information. parameter 85 ns speed jedec std description min typ max unit t avav t wc write cycle time (note 1) 85 ns t avwl t as address setup time (we# to address) 0 ns t aso address setup time to ce#f low during toggle bit polling 15 ns t elax t ah address hold time 45 ns t aht address hold time from ce#f or oe# high during toggle bit polling 0ns t dveh t ds data setup time 45 ns t ehdx t dh data hold time 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) 0ns t wlel t ws we# setup time 0 ns t ehwh t wh we# hold time 0 ns t eleh t cp ce#f pulse width 35 ns t ehel t cph ce#f pulse width high 35 ns t whwh1 t whwh1 programming operation (note 2) byte 5 s word 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) 4s t whwh2 t whwh2 sector erase operation (note 2) 0.7 sec
ds42587 49 ac characteristics t ghel t ws oe# ce#f we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 27. flash alternate ce#f controlled write (erase/program) operation timings
50 ds42587 ac characteristics sram read cycle note: ce1#s = oe# = v il , ce2s = we# = v ih , ub#s and/or lb#s = v il figure 28. sram read cycle ? address controlled parameter symbol description min max unit t rc read cycle time 85 ns t aa address access time 85 ns t co1 , t co2 chip enable to output 85 ns t oe output enable access time 45 ns t ba lb#s, ub#s to valid output 85 ns t lz1 , t lz2 chip enable (ce1#s low and ce2s high) to low-z output 10 ns t blz ub#, lb# enable to low-z output 10 ns t olz output enable to low-z output 5 ns t hz1 , t hz2 chip disable to high-z output 0 25 ns t bhz ub#s, lb#s disable to high-z output 0 25 ns t ohz output disable to high-z output 0 25 ns t oh output data hold from address change 15 ns ddress ata out previous data valid data valid t aa t rc t oh
ds42587 51 ac characteristics figure 29. sram read cycle notes: 1. we# = v ih , if cios is low, ignore ub#s/lb#s timing. 2. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. data valid high-z t rc cs#1 address ub#, lb# oe# data out t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz cs2 t co2
52 ds42587 ac characteristics sram write cycle notes: 1. we# controlled, if cios is low, ignore ub#s and lb#s timing. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 30. sram write cycle ? we# control parameter symbol description min max unit t wc write cycle time 85 ns t cw chip enable to end of write 70 ns t as address setup time 0 ns t aw address valid to end of write 70 ns t bw ub#s, lb#s to end of write 70 ns t wp write pulse time 60 ns t wr write recovery time 0 ns t whz write to output high-z 0 25 ns t dw data to write time overlap 35 ns t dh data hold from write time 0 ns t ow end write to output low-z 5 ns address cs1#s data undefined ub#s, lb#s we# data in data out t wc t cw (see note 2) t aw high-z high-z data valid cs2s t cw (see note 2) t bw t wp (see note 5) t as (see note 4) t wr (see note 3) t bw t dw t dh t ow
ds42587 53 ac characteristics notes: 1. ce1#s controlled, if cios is low, ignore ub#s and lb#s timing. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 31. sram write cycle ? ce1#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t as (see note 2 ) t bw t cw (see note 3) t wr (see note 4) t wp (see note 5) t dw t dh
54 ds42587 ac characteristics notes: 1. ub#s and lb#s controlled, cios must be high. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 32. sram write cycle ? ub#s and lb#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t bw t dw t dh t wr (see note 3) t as (see note 4) t cw (see note 2) t cw (see note 2) t wp (see note 5)
ds42587 55 flash erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 12 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. flash latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. package pin capacitance note: 7.test conditions t a = 25 c, f = 1.0 mhz. flash data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 49 sec byte program time 5 150 s excludes system level overhead (note 5) word program time 7 210 s accelerated byte/word program time 4 120 s chip program time (note 3) byte mode 21 63 sec word mode 14 42 description min max input voltage with respect to v ss on all pins except i/o pins (including oe#, and reset#) ? 1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ? 1.0 v v cc + 1.0 v v cc current ? 100 ma +100 ma parameter symbol description test setup typ max unit c in input capacitance v in = 0 11 14 pf c out output capacitance v out = 0 12 16 pf c in2 control pin capacitance v in = 0 14 16 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
56 ds42587 sram data retention note: ce1#s v cc ? 0.2 v, ce2s v cc ? 0.2 v (ce1#s controlled) or ce2s 0.2 v (ce2s controlled), cios = v ss or v cc . figure 33. ce1#s controlled data retention mode figure 34. ce2s controlled data retention mode parameter symbol parameter description test setup min typ max unit v dr v cc for data retention cs1#s v cc ? 0.2 v (see note) 1.5 3.3 v v dh data retention current v cc = 1.5 v, ce1#s v cc ? 0.2 v (see note) 0.5 5 a t sdr data retention set-up time see data retention waveforms 0ns t rdr recovery time t rc ns v dr v cc 2.7v 2.2v ce1#s gnd data retention mode ce1#s v cc - 0.2 v t sdr t rdr v cc 2.7 v 0.4 v v dr ce2s gnd data retention mode t sdr t rdr ce2s 0.2 v
ds42587 57 physical dimensions flb073 ? 73-ball fine-pitch grid array 8 x 11 mm
58 ds42587 revision summary revision a (june 18, 2001) initial release as a data sheet. ? trademarks copyright ? 2001 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

▲Up To Search▲

Price & Availability of AM29DL323D

	To Download AM29DL323D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .